Semiconductor device

ABSTRACT

The present invention provides a semiconductor device having a stacked structure which realizes the miniaturization of a contour size and the reduction of thickness. The present invention also provides a semiconductor device which realizes high performance and high reliability in addition to the miniaturization of the contour size. The semiconductor device uses a package substrate on which bonding leads which are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads are formed. The semiconductor device further includes an address output circuit and a data input/output circuit which are also served for memory access and a signal processing circuit having a data processing function. A semiconductor chip in which bonding pads which are connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads which are connected to the bonding leads corresponding to the data terminals of the package substrate are distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device, and moreparticularly to a technique which is effectively applicable to asemiconductor device in which a plurality of semiconductor chips aremounted on a package substrate in a laminated or stacked structure, forexample.

[0002] In a stacked LSI (Large-sized Integrated Circuit) which assemblessemiconductor chips on a package substrate in a laminated or stackedstructure, existing semiconductor chips are combined in many cases andcommon signals and power source/ground are connected via wiring layersof a package. Due to a prior art search which is carried out after thepresent invention was made, as a prior art related to the presentinvention, a technique disclosed in Japanese Unexamined PatentPublication 43531/2000 is reported. However the technique disclosed inthis publication aims at the reduction of time and efforts necessary fordesigning and development of types of standard package LSI and lacksdeliberation to miniaturizing of the package and thinning of a contoursize of the package substrate which will be explained later.

SUMMARY OF THE INVENTION

[0003] With respect to the common signals and power source/ground in twochips which constitute the stacked package LSI, their pads are notalways arranged to positions where they can be connected easily betweenthe chips. Accordingly, even when the wiring layers are connected on thepackage substrate, in many cases, there exist crossing wiring layers orwiring layers are arranged densely. In these cases, the number of wiringlayers of the package substrate is increased or a contour size isincreased thus obstructing the miniaturization and thinning of thesemiconductor device. Since connection terminals of mounting chips areformed individually, a large terminal arrangement area becomes necessaryand this also becomes a cause of increasing the contour size of thepackage.

[0004]FIG. 19 to FIG. 21 show examples of stacked package LSI which isreviewed prior to arriving at the present invention. A microcomputer LSIand a memory LSI are respectively constituted of existing semiconductorchips. In FIG. 19, the microcomputer LSI, the memory LSI and a packagesubstrate which constitute the stacked package LSI are respectivelyshown. The microcomputer LSI and the memory LSI are respectivelyconstituted of the existing semiconductor chips. FIG. 20 shows anappearance of the stacked package LSI after mounting the memory LSI andthe microcomputer LSI onto the substrate and, thereafter, performingbonding wiring. FIG. 21 a cross-sectional view of the stacked packageLSI shown in FIG. 20.

[0005] As shown in FIG. 19 to FIG. 21, the stacked package LSI adoptsthe structure which is formed as follows. The memory LSI is die-bondedto the package substrate made of glass epoxy-based resin. Then, themicrocomputer LSI is die-bonded to the memory LSI in a superposed mannerand respective chips and the substrates are connected to each other bywire bonding. Thereafter, these components are molded by resin andsolder balls are formed on back-surface terminal portions.

[0006] In FIG. 19, address terminals and data terminals which areconnected with memories or the like are collectively arranged at sidesof the microcomputer LSI which are disposed close to each other. Due tosuch a constitution, when the microcomputer LSI, the memory LSI and thelike are mounted on the substrate in plane, it is possible to arrange anaddress bus and a data bus directed to the memory and the like on thesubstrate with the shortest distance therebetween and in a collectivemanner. On the other hand, with respect to the memory LSI, in view ofthe characteristics thereof that the number of terminals is small andcorresponding to the external terminal arrangement of a standardpackage, the address terminals are mainly arranged at one side and thedata terminals are arranged at another side which faces one side in anopposed manner.

[0007] When the above-mentioned microcomputer LSI and memory LSI onwhich the bonding pads are arranged respectively are stacked orlaminated to the package substrate and the directions of the addressterminals of the microcomputer LSI and the memory LSI are aligned, forexample, the directions of data terminals of the microcomputer LSI andthe memory LSI are not aligned and hence, it is necessary to pull aroundwiring layers on the package substrate for wiring connection. Further,also with respect to the aligned address terminals, the pitch of bondingpad arrangement differs between the microcomputer LSI and the memory LSIand hence, it may be necessary to form terminals on the microcomputerLSI and the memory LSI independently from each other in most cases.

[0008] Accordingly, in the package substrate, the number of bondingterminals (bonding leads) is increased and hence, the bonding leadscannot be arranged in a row and it is necessary to arrange the bondingleads in two rows as in the case of the example shown in FIG. 20. Thisarises a drawback that the contour size of the package substrate isenlarged. Further, depending on the arrangement of terminals of themicrocomputer LSI and the memory LSI to be connected to each other,there arises a case in which wiring layers on the package substratecross each other and hence, it is necessary to provide a multi-layeredprinted wiring board. This also gives rise to a drawback that thethickness as one of contour sizes is also increased.

[0009] It is an object of the present invention to provide asemiconductor device having the stacked structure which can realizeminiaturization and thinning of contour sizes.

[0010] It is another object of the present invention to provide asemiconductor device which can realize high performance and highreliability in addiction to the miniaturization of the contour size. Theabove-mentioned and other objects and novel features of the presentinvention will become apparent from the description of thisspecification and attached drawings.

[0011] To briefly describe the summary of typical inventions out ofinventions disclosed in the present invention, they are as follows.

[0012] According to one aspect of the present invention, a semiconductordevice uses a package substrate which includes bonding leads which areformed respectively corresponding to bonding pads for address andbonding pads for data which are distributed to a first side and a secondside of a memory chip facing each other in an opposes manner, andaddress terminals and data terminals which are connected to the bondingleads. A semiconductor chip includes an address output circuit and adata input/output circuit which are also served for memory access and asignal processing circuit having a data processing function, wherein thebonding pads which are connected to the bonding leads corresponding tothe address terminals and the bonding pads which are connected to thebonding leads corresponding to the data terminals are distributed to andarranged on two sides out of four sides of the package substrate. Thesemiconductor chip and the memory chip are mounted on the packagesubstrate in a stacked structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a view showing the constitution of a microcomputer LSI,a memory LSI and a package substrate for explaining one embodiment of astacked package LSI according to the present invention.

[0014]FIG. 2 is an appearance view of the semiconductor device aftermounting the memory LSI and the microcomputer LSI on the substrate shownin FIG. 1 and performing wire bonding thereafter.

[0015]FIG. 3 is a cross-sectional view of one embodiment of the stackedpackage LSI shown in FIG. 2.

[0016]FIG. 4 is a top plan view showing another embodiment of thepackage substrate used by the present invention.

[0017]FIG. 5 is a top plan view showing another embodiment of thepackage substrate used by the present invention.

[0018]FIG. 6 is an appearance view of the semiconductor device aftermounting the memory LSI and the microcomputer LSI on the substrate shownin FIG. 5 and performing wire bonding thereafter.

[0019]FIG. 7 is a top plan view showing another embodiment of thepackage substrate used by the present invention.

[0020]FIG. 8 is an appearance view of the semiconductor device aftermounting the memory LSI and the microcomputer LSI on the substrate shownin FIG. 7 and performing wire bonding thereafter.

[0021]FIG. 9 is a top plan view showing another embodiment of thepackage substrate used by the present invention.

[0022]FIG. 10 is an appearance view of the semiconductor device aftermounting the memory LSI and the microcomputer LSI on the substrate shownin FIG. 9 and performing wire bonding thereafter.

[0023]FIG. 11 is a partial appearance view showing another embodiment ofthe semiconductor device according to the present invention.

[0024]FIG. 12 is a partial appearance view showing another embodiment ofthe semiconductor device according to the present invention.

[0025]FIG. 13 is a partial appearance view showing another embodiment ofthe semiconductor device according to the present invention.

[0026]FIG. 14 is a block diagram showing one embodiment of amicrocomputer LSI used in the present invention.

[0027]FIG. 15 is a view schematically showing an arrangement of pins forexplaining one embodiment of the microcomputer LSI in FIG. 14.

[0028]FIG. 16 is an appearance view after mounting the memory LSI andthe microcomputer LSI on the substrate of one embodiment of thesemiconductor device according to the present invention and performingwire bonding thereafter.

[0029]FIG. 17 is a partially enlarged view of FIG. 16.

[0030]FIG. 18 is a top plan view showing one embodiment of the packagesubstrate used in the semiconductor device shown in FIG. 16.

[0031]FIG. 19 is a view showing the constitution of a microcomputer LSI,a memory LSI and a package substrate for explaining one embodiment of astacked package LSI which is reviewed prior to the present invention.

[0032]FIG. 20 is an appearance view of the semiconductor device aftermounting the memory LSI and the microcomputer LSI on the substrate shownin FIG. 19 and performing wire bonding thereafter.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0033] In FIG. 1 to FIG. 3, the constitution of one embodiment of astacked package LSI according to the present invention is shown. Thatis, in FIG. 1, a microcomputer LSI, a memory LSI and a package substratewhich constitute the stacked package LSI are respectively shown. In FIG.2, an appearance of the stacked package LSI in a state that the memoryLSI and the microcomputer LSI are mounted on the substrate and,thereafter, the wire bonding is performed is shown. FIG. 3 shows thecross section of the stacked package LSI. As shown in FIG. 1 to FIG. 3,the stacked package LSI of this embodiment has the structure which isformed as follows. That is, the memory LSI is die-bonded to the packagesubstrate made of glass epoxy resin. Then, the microcomputer LSI issuperposed on and is die-bonded to the memory LSI. Wire bonding isperformed between the respective chips and the substrate. Thereafter,the respective chips and the substrate are molded with resin and solderballs are formed on back-surface terminal portions.

[0034] In FIG. 1, while the memory LSI is constituted of an existingsemiconductor chip, the arrangement of bonding pads of the microcomputerLSI is determined corresponding to the memory LSI which is combined withthe microcomputer LSI. The microcomputer LSI is configured to constitutea so-called ASIC (Application Specified Integrated Circuit), that is, aspecific-use IC. In the semiconductor integrated circuit device, toeasily constitute the ASIC in which a plurality of circuit blocks aremounted around a CPU (central processing unit), respective circuitblocks are formed into so-called modules or macro cells as independentcircuit functional units. The magnitude and constitution of eachfunctional unit can be changed. Setting of the arrangement of thebonding pads of the microcomputer LSI corresponding to theabove-mentioned combination of the microcomputer LSI with the memory LSIis performed along with layout designing of the functional blockscorresponding to the combination of the above-mentioned functionalunits.

[0035] With respect to the package substrate (wiring substrate), thearrangement of boding leads (wire connecting portions) is setcorresponding to the arrangement of the above-mentioned bonding padsbetween the microcomputer LSI and the memory LSI. The above-mentionedpackage substrate includes a base substrate made of glass epoxy resin,for example, a plurality of copper wiring layers which are formed on anupper surface and a lower surface thereof, insulation films (solderresist films) which cover surfaces of the above-mentioned plurality ofcopper wiring layers at portions other than the above-mentioned wireconnecting portions and external terminal connecting portions (bumplands), and through-hole wiring layers which connect a plurality ofcopper wiring layers formed on the above-mentioned upper surface andlower surface to each other.

[0036] The memory LSI is, although it is not particularly limited, astatic type RAM which has a storage capacitance of approximately 8Mbits. The shape of the semiconductor chip is formed into a rectangularshape and address and data are distributed to short sides where bondingpads are formed. Compared to the memory LSI having such a constitution,the microcomputer LSI has a substantially square chip shape and has acontour size smaller than that of the above-mentioned LSI. Accordingly,as mentioned above, the stacked package LSI is constituted such that thememory LSI is die-bonded to the package substrate, the microcomputer LSIis superposed on and is die-bonded to the memory LSI, and wire bondingis performed between respective chips and the substrate.

[0037] To reduce the contour size, the above-mentioned package substrateis formed into a substantially square shape to ensure the largest areawith respect to the outer circumference. In such a constitution, thereexists no area margin at the short sides of the memory LSI and hence,the bonding leads which are indicated by a rectangular shape arearranged along the outer circumference, and the pullout direction ofwiring layers reaching the through holes is directed to the inside ofthe package substrate. With respect to the bonding leads whichcorrespond to the above-mentioned address and data through holescorresponding to the bonding leads are arranged at the inside of thesubstrate. On the contrary, since there exists area margin at long sidesof the memory LSI, the through holes are arranged such that they aredistributed alternately at both sides of the bonding leads to sandwichthe bonding leads.

[0038] As described above, in the microcomputer LSI, the addressterminals and the data terminals are arranged in a concentrated manneron the sides which face each other. Further, a group of terminals whichdo not contribute to the connection with the memory LSI are mainlyarranged on sides other than the above-mentioned sides. Accordingly, thepossibility that the directions of terminals which are connected to eachother are not aligned even when the microcomputer LSI is stacked on thememory LSI is eliminated. Further to prevent the wires from crossingeach other in a complicated manner at the time of performing stackingand bonding, the microcomputer LSI has a pitch thereof adjusted inconformity with a pitch of the terminals of the memory LSI. That is,compared to a case in which the wires cross each other in a complicatedmanner, that is, a case in which three wires are superposed in thevertical direction as shown in FIG. 21, for example, a case in which twowires are superposed by eliminating crossing as shown in FIG. 3 canreduce a thickness of a mold (sealed resin body).

[0039] Although the above-mentioned pitch adjustment can be performed bysimply adjusting the distance, in this embodiment, the pitch adjustmentis performed by arranging terminals having other functions to the row ofaddress terminals or the row of data terminals. Since the pitchadjustment is performed in this manner, the terminals of themicrocomputer LSI and the terminals of the memory LSI which are to beconnected to each other can be bonded to the same substrate-side pads,whereby it is unnecessary to pull around wiring layers for connectingbetween the terminals on the package substrate. As a result, it isenough for the package substrate to have wiring connection from thebonding leads to ball terminals for external connection and hence, thesufficient required functions can be performed by the two-layered wiringlayers formed on a front surface and a back surface of the substrate.The constitution provided with such a pitch adjustment contributes tothinning of the stacked package LSI along with thinning of theabove-mentioned mold. Since the bonding leads are substantially used incommon by the microcomputer LSI and the memory LSI, the number of leadscan be suppressed to a necessary minimum whereby the contour size can beminiaturized.

[0040] With respect to the leads of the sides which are bonded in commonby the microcomputer LSI and the memory LSI, the length of the leads iselongated such that the wires which are directed and connected to themicrocomputer LSI and the memory LSI can be bonded in parallel in thevertical direction. On the other hand, as in the case of the bondingleads which correspond to the long sides of the memory LSI, the leads onthe sides to which only the microcomputer LSI is bonded, is retained toa length which allows bonding of one wire thus preventing the wiringlayer region from becoming large more than necessary.

[0041] Although the length of the bonding leads is changed in accordancewith every side in this embodiment, the length of the bonding leads maybe changed in accordance with a plurality of leads to be bonded withoutchanging the length of the bonding leads in accordance with every side.Another characteristics of this embodiment related to theminiaturization lies in that, since the memory chip has a rectangularshape as described above, the side on which the bonding leads of thememory chip are arranged has no margin in the contour size, whereby thebonding leads are arranged at the outermost circumference and thethrough holes are arranged to be directed to the inner circumference. Onthe other hand, with respect to the sides to which only the microchip isbonded, the through holes are arranged such that they are distributed tothe inside and the outside of the bonding leads.

[0042]FIG. 4 is a top plan view showing another embodiment of thepackage substrate used in the present invention. In the above-mentionedembodiment shown in FIG. 1, the addresses or data of the memory LSI andthe microcomputer LSI are completely arranged on the same sides.However, in view of the relationship with the layout of the chips, theaddresses and the data are not always concentrated on the sides whichface each other in an opposed manner. Further, even when the addressesand data are completely separated at the sides which face each other inan opposed manner, signals for control, for example, control signalssuch as read/write signals, chip select signals and output enablesignals which the microcomputer and the memory use do not always agreewith each other.

[0043] In this embodiment, with respect to the microcomputer LSI and thememory LSI, when the same terminals or the terminals (bonding pads) tobe connected with each other are arranged on the sides which face eachother in an opposed manner, wiring layers which bridge the opposingsides are formed on the substrate. By concentrating the most signals(addresses and data) to be connected to each other by the microcomputerLSI and the memory LSI to the same sides, the number of bridging wirelayers can be minimized. Accordingly, it is possible to sufficientlyperform the required function using two-layered wiring which are formedon the front surface and the back surface of the substrate.

[0044]FIG. 5 is a top plan view of another embodiment of the packagesubstrate used in the present invention. This embodiment is directed tothe shape of the bonding leads. The embodiment shown in FIG. 5 shows anexample of the package substrate in which the rectangular bonding leadsare arranged in the same manner as the embodiment shown in FIG. 1. FIG.6 shows an appearance of a stacked package LSI in which a memory LSI anda microcomputer LSI are mounted on a package substrate in a stackedmanner. The embodiment shown in FIG. 6 also corresponds to theembodiment shown in FIG. 2.

[0045] In this embodiment, with respect to bonding leads which performwire bonding in common between the memory LSI and the microcomputer LSI,to bond at least two wires to the bonding lead, it is necessary toconnect wires of the microcomputer LSI to the deep side of the lead(outside of the lead). Then, as a result of the arrangement in which thebonding pads of the microcomputer LSI are arranged collectively atportions close to the center of the substrate, the wires are directed inthe radial direction such that they are concentrated at positions closeto the center of the substrate. As a result, there arise portions of thewires which pass over another neighboring leads thus giving rise to aproblem that the potential of short circuiting between the neighboringlead and the wire is high.

[0046]FIG. 7 is a top plan view showing another embodiment of thepackage substrate used in the present invention. This embodiment isdirected to a method for obviating the problem that there arise portionsof wires which are bonded while passing over another neighboring leadsas in the embodiment shown in FIG. 5. In this embodiment, by taking thedirection of wires which are served for connection between the bondingleads and the corresponding bonding pads of the microcomputer LSI andthe memory LSI into consideration, the bonding leads are arranged in anoblique manner. FIG. 8 shows an appearance of a stacked package LSI inwhich the memory LSI and the microcomputer LSI are mounted on thepackage substrate in a stacked manner and wire bonding is performedthereafter.

[0047] In FIG. 8, with respect to the bonding leads which performbonding in common with respect to the memory LSI and the microcomputerLSI, at least two wires are arranged in a radial direction such thatthey are directed toward the corresponding bonding pads of themicrocomputer LSI and the memory LSI. Here, by making this direction andthe longitudinal direction of the bonding leads substantially identicalto each other, it is possible to eliminate portions of the wires whichare bonded while passing over another neighboring leads. Further, at thesame time, it is possible to prevent the wires from crossing each otherin a complicated manner so that only two wires at the maximum whichcorrespond to the microcomputer LSI and the memory LSI are superposedeach other whereby a thickness of a mold can be reduced.

[0048]FIG. 9 is a top plan view showing another embodiment of thepackage substrate used in the present invention. This embodiment isdirected to a method for obviating the problem that there arise portionsof the wires which are bonded while passing over another neighboringleads as in the embodiment shown in FIG. 5. In this embodiment, portionsof the neighboring leads over which the wires pass are notched andhence, it is possible to shorten a pitch of the leads to a necessaryminimum while reducing the potential of short-circuiting between theneighboring leads and the wires. FIG. 10 shows an appearance of astacked package LSI in which the memory LSI and the microcomputer LSIare mounted on the package substrate in a stacked manner and wirebonding is performed thereafter.

[0049] In FIG. 10, as mentioned previously, with respect to the bondingleads which perform bonding in common with respect to the memory LSI andthe microcomputer LSI, at least two wires are arranged in a radialdirection such that they are directed toward the corresponding bondingpads of the microcomputer LSI and the memory LSI and hence, it isnecessary to connect the wires of the microcomputer LSI to the deep sideof the bonding lead (outside of the bonding lead). As a result, therearise portions of the wires which are bonded while passing over anotherneighboring leads and hence, the potential of short-circuiting betweenthe neighboring lead and the wire is increased. However, in thisembodiment, the portion of the leads over which the neighboring wirespass are notched and hence, it is possible to obviate a drawback onshort-circuiting between the neighboring leads and the wires.

[0050]FIG. 11 is a partial appearance view of another embodiment of thesemiconductor device according to the present invention. In thisembodiment, a portion of the appearance when one semiconductorintegrated chip LSI is mounted on a package substrate is shown in anillustrated manner. In this embodiment, with respect to thesemiconductor chip mounted on the package substrate, one semiconductorchip LSI is mounted. It is needless to say that this embodiment isapplicable to the structure in which another semiconductor chip ismounted on the semiconductor chip LSI in a stacked manner.

[0051] This embodiment is applicable to a case in which the number ofbonding pads formed on the semiconductor chip LSI is large and hence,the bonding leads can not be arranged in a row on the substrate. In thiscase, the bonding leads are arranged in two rows, wherein the inside rowand the outside row are alternately arranged thus constituting aso-called staggered arrangement. This embodiment is provided foreliminating the superposition of the neighboring wires which connect thebonding leads and the bonding pads and for ensuring regions for formingwiring layers which extend from outside bonding leads to the throughholes formed inside.

[0052]FIG. 12 is a partial appearance view showing another embodiment ofthe semiconductor device according to the present invention. Thisembodiment relates to an improvement of the embodiment shown in FIG. 11,wherein a portion of the appearance of the semiconductor device in astate that one semiconductor chip LSI is mounted on the packagesubstrate is shown in an illustrated manner. In the embodiment shown inFIG. 11, there arise portions of the wires which extend from the outsidebonding leads and are bonded while passing over another leads in theinside and hence, there is a possibility that the potential ofshort-circuiting between the inside leads and the wires is increased.

[0053] In this embodiment, to obviate such a drawback, by consideringthe direction of the wires which are served for connecting the bondingleads and the corresponding pads of the semiconductor chip LSI, thebonding leads are arranged in an oblique manner. By arranging thebonding leads and the wires which are connected to the bonding leads inthe radial direction such that they are aligned substantially in thesame direction, it is possible to eliminate portions where the wires arebonded while passing over another leads disposed inside. Further, at thesame time, it is possible to eliminate crossing of the wires to eachother and hence, short circuiting of the wires can be prevented and thethickness of a mold can be reduced.

[0054]FIG. 13 is a partial appearance view of another embodiment of thesemiconductor device according to the present invention. This embodimentrelates to an improvement of the embodiment shown in FIG. 12. In FIG.13, a portion of the appearance of the semiconductor device when onesemiconductor chip LSI is mounted on a package substrate is shown in anillustrated manner. In the embodiment shown in FIG. 12, when the leadsare arranged in a multiple rows and the inclination of the leads isaligned to the wire direction, as the leads extend toward the outside,the distance between leads is widened. On the contrary, the distance atcorner portions of the inner leads is narrowed and hence, there arises acase that the wiring layers extending from the outside leads to thethrough holes can not pass over. To obviate such a drawback, in thisembodiment, inner circumferential corner portions of the leads which areexpanded in the radial direction are notched so as to ensure the spacehaving a width necessary for allowing the wiring layers to pass. Due tosuch a constitution, it is possible to pull around the wire layerswithout expanding the bonding area more than necessary.

[0055]FIG. 14 is a block diagram showing one embodiment of amicrocomputer LSI used in the present invention. Respective circuitblocks in the drawing are formed on one substrate made of singlecrystalline silicon using a known fabrication technique of CMOS(complementary MOS) semiconductor integrated circuits.

[0056] Although the above-mentioned microcomputer LSI is notspecifically limited, the microcomputer LSI realizes high-performancearithmetic processing using a RISC (Reduced Instruction Set Computer)type central processing unit CPU, integrates necessary peripheralequipment for system constitution and is directed to portable equipmentapplication. The central processing unit CPU has a command set of RISCtype, wherein basic commands are operated at 1 state by 1 command (1system clock cycle) by performing the pipe-line processing. Using thesecenter processing unit CPU and data signal processor DSP mainly,following peripheral circuits are mounted to constitute a mobiletelephone set, for example.

[0057] The inner bus includes an I bus, a Y bus, an X bus, an L bus andperipheral buses. To constitute a user system using a least number ofparts, as built-in peripheral modules, a memory XYMEM which is directedto image processing and a memory controller XYCNT are provided. Thesememory XYMEM and memory controller XYCNT are connected to the I bus, theX bus, the Y bus and the L bus and data inputting/outputting of imageprocessing and data outputting operation for display operation areperformed.

[0058] In the above-mentioned I bus, a cache memory CACHE, a cachememory controller CCN, a memory management controller MMU, a translationlook-aside buffer TLB, an interrupt controller INTC, a clockoscillator/watch dog timer CPG/WDT, a video I/O module VIO and anexternal bus interface are provided. These are connected with theabove-mentioned memory LSI via the external bus interface.

[0059] To the L bus, the cache memory CACHE, the cache memory controllerCCN, the memory management controller MMU, the translation look-asidebuffer TLB, the central processing unit CPU, data signal processor DSP,a user break controller UBC and an advanced user debugger AUD areconnected.

[0060] To the peripheral bus, a 16-bit timer unit TMU, a compare matchtimer CMT, a serial I/O (with FIFO) SIOFO, a FIFO built-in serialcommunication interface SCIF1, an I²C controller I²C, a multi-functionalinterface MFI, a NAND/AND flush interface FLCTL, a user debug interfaceH-UDI, an ASE memory ASERAM, a pin function controller PFC, and a RCLKoperation watch dog timer RWDT are connected. To the above-mentionedperipheral bus and the I bus, a bus state controller BSC and a directmemory access controller DMAC are connected.

[0061]FIG. 15 is a view showing the approximate pin arrangement of oneembodiment of the microcomputer LSI shown in FIG. 14. In thisembodiment, while there are provided 176 pieces of pins (bonding pads)in total, the pins which are connected to the memory LSI are indicatedby black dots. In the same manner as the microcomputer LSI shown in FIG.1, the pins which correspond to addresses and data are arranged suchthat they are distributed to upper and lower sides which face each othervertically. In this embodiment, the pins corresponding to data arearranged on the upper side and the pins corresponding to the addressesare arranged on the lower side. To match a pitch of the correspondingpins (bonding pads) of the memory LSI on which the microcomputer LSI ismounted, pins which are connected only to the microcomputer LSI aresuitably arranged between the black-dotted pins which are connected tothe above-mentioned LSI.

[0062] Although not shown in the drawing, with respect to the pinsprovided to the microcomputer LSI, the pins A0 to A25 are served foraddresses and D0 to D15 are served for data. Besides the above, as apower source system, a plurality of power source voltages VCC and aplurality of ground potentials VSS are provided respectively. In thepower source system, a digital circuit for reducing an influence ofnoises is divided into an output circuit for performing outputting ofsignals to external terminals and an inner circuit. Further, independentpower source pins are provided for a circuit which handles analoguesignals.

[0063] The memory LSI has storage capacitance of approximately 8 Mbitsand performs a memory access per 16 bits and hence, the address includes19 bits from A0 to A18. Although the microcomputer LSI includes 26addresses A0 to A25, the addresses which are connected in common withthe microcomputer LSI and the memory LSI are 19 pieces and hence, thenumber of addresses becomes 19+16=35 pieces including addresses fordata.

[0064] Although not particularly limited, as control signals which areconnected in common, there are provided four signals consisting of asignal WE (write enable), a signal OE (output enable), a signal US(upper select) and a signal LS (low select). The signal US is served forinstructing writing of upper 8 bits out of 16-bit data and the signal LSis served for instructing writing of lower 8 bits out of 16-bit data.Accordingly, the number of pins which are connected in common by themicrocomputer LSI and the memory LSI is small, that is, 39 pieces intotal. Accordingly, to match the arrangement of the pins which areconnected in common in the above-mentioned manner in the memory LSI, inthe microcomputer LSI, the bonding pads for data and the bonding padsfor address are arranged in a skipped manner as indicated by black dotsin the drawing.

[0065]FIG. 16 shows an appearance of one embodiment of the semiconductordevice according to the present invention in a state that the memory LSIand the microcomputer LSI are mounted on the substrate and, thereafter,wire bonding is performed. In this embodiment, the stacked package LSIon which the microcomputer LSI which is explained in conjunction withFIG. 14 and FIG. 15 and the memory LSI formed of an approximately 8Mbits SRAM are mounted is shown. In the drawing, balls formed on a backsurface of the package substrate are indicated by white dots.

[0066] In this embodiment, out of the bonding leads mounted on thesubstrate, with respect to the bonding leads which are matted in black,the wires extend from these bonding leads to the memory LSI and themicrocomputer LSI and are connected in common. FIG. 17 is a partialenlarged view, wherein the bonding leads are arranged obliquely alongthe extension direction of the wires such that the wires extendingtoward the memory LSI and the microcomputer LSI from the bonding leadsdo not cross each other. First, this constitution prevents the wiresextending from the neighboring leads from crossing above the bondingleads.

[0067]FIG. 18 is a top plan view of one embodiment of the packagesubstrate used in the semiconductor device shown in FIG. 16. The bondingleads which include the data terminals and address terminals of theabove-mentioned memory LSI and the microcomputer LSI are formed on theupper side and a lower side of the substrate. The bonding leads whichare formed on the upper and lower sides are arranged along the outermostcircumference. On the other hand, with respect to the bonding leadswhich are connected to only the microcomputer LSI, the through holes areformed in a dispersed manner at the left and the right with respect tothe bonding leads. That is, in the left and right sides, the throughholes are formed at the outermost circumference. The number of thethrough holes which are dispersed to the left and right with respect tothe above-mentioned bonding leads is not univocally alternately anduniformly divided as in the case of the embodiment shown in FIG. 1. Thatis, the number of the through holes is suitably determined byconsidering the space over the substrate.

[0068] In the above-mentioned embodiment, it is possible to suppress thepull around of wiring layers on the substrate package to a minimum andhence, it is possible to make the contour size as small as possible. Dueto the elimination of crossing wiring layers, the connection of packagewiring layers can be performed at both of the front and rear layers andhence, it is possible to use the thin and inexpensive substrate.Further, it is also possible to reduce the thickness of the mold portionby suppressing crossing of wires. Incidentally, when the semiconductordevice is constituted as shown in FIG. 19 which is studied prior to thepresent invention, LFBGA can be obtained only at a level of 1.4 mmsquare. According to the constitution shown in FIG. 16, it is possibleto realize the semiconductor device which is smaller than thesemiconductor device shown in FIG. 19 by one rank such that the TFBGAcan be arrayed at 1.2 mm square.

[0069] Although the inventions which have been made by the inventors arespecifically explained in conjunction with several embodiments, it isneedless to say that the present invention is not limited to theabove-mentioned embodiments and various modifications are conceivablewithout departing from the gist of the present invention. For example,the memory LSI may be, besides the above-mentioned SRAM, a dynamic RAMor a flush memory (EEPROM). The microcomputer LSI may be any type ofdigital signal processing circuit including a microprocessor or thelike. The present invention is, besides the above-mentioned stackedpackage LSI, widely applicable to a semiconductor device which mountsone semiconductor chip on a substrate and adopts a package of BGAconstitution.

[0070] To briefly explain advantageous effects obtained by typicalinventions among the inventions disclosed by the present application,they are as follows. The semiconductor device uses the package substrateon which the bonding leads which are formed respectively correspondingto bonding pads for address and data which are distributed to theopposing first and second sides of the memory chip, and the addressterminals and data terminals which are connected to the bonding leadsare formed. The semiconductor device further includes the address outputcircuit and data input/output circuit which are also served for memoryaccess and the signal processing circuit having the data processingfunction. The semiconductor chip in which the bonding pads which areconnected to the bonding leads corresponding to the address terminals ofthe package substrate and the bonding pads which are connected to thebonding leads corresponding to the data terminals of the packagesubstrate are distributed to two sides out of four sides and theabove-mentioned memory chip are mounted on the package substrate in astacked structure. Accordingly, it is possible to suppress thepull-around of wiring layers on the substrate package to a minimum. Itis also possible to make the contour size of the semiconductor device assmall as possible. Further, since the connection of wiring layers can beperformed both of the front and rear layers, it is possible to use thethin and inexpensive substrate.

What is claimed is:
 1. A semiconductor device comprising: a memory chipincluding bonding pads which are arranged along a first sidecorresponding to address terminals and bonding pads which are arrangedalong a second side which faces the first side in an opposed mannercorresponding to data terminals; a package substrate including bondingleads which are formed corresponding to the first side of the memorychip, bonding leads which are formed corresponding to the second side ofthe memory chip, and address terminals and data terminals which areconnected to the bonding leads; a semiconductor chip which includes anaddress output circuit and a data input/output circuit which are alsoserved for memory access and a signal processing circuit having a dataprocessing function, wherein bonding pads which are connected to thebonding leads of the package substrate corresponding to the addressterminals and bonding pads which are connected to the bonding leads ofthe package substrate corresponding to the data terminals are arrangedso as to be distributed to two sides out of four sides, wherein thememory chip and the semiconductor chip are mounted on the packagesubstrate in a stacked structure.
 2. A semiconductor device according toclaim 1, wherein the corresponding terminals of the semiconductor chipand the memory chip are connected to each other by wires with respect tothe bonding leads which are formed in common on the package substrate.3. A semiconductor device according to claim 1, wherein in conformitywith pitches of respective bonding pads of address and data of thememory chip, the respective bonding pads of the corresponding addressand data of the semiconductor chip are arranged, and wherein between therespective bonding pads for address and data of the semiconductor chip,bonding pads which are independently formed on the semiconductor chip soas to conform to the memory-chip side pitch are suitably arranged.
 4. Asemiconductor device according to claim 1, wherein the package substrateforms wiring layers respectively on a front surface on which thesemiconductor chip is mounted and on a back surface on which ballsconstituting external terminals are formed, and corresponding wiringlayers are connected by through holes.
 5. A semiconductor deviceaccording to claim 4, wherein the semiconductor chip constitutes a onechip microcomputer, and wherein bonding pads which are connected toexternal terminals necessary for the microcomputer are also arranged onremaining two sides out of four sides.
 6. A semiconductor deviceaccording to claim 5, wherein the memory chip has an area larger than anarea of the semiconductor chip and is formed into a rectangular shape inwhich a length of the first side and the second side is shorter than alength of other two sides, and wherein with respect to rows of thebonding leads which are formed corresponding to the first side and thesecond side of the memory chip, the pull-out directions of wiring layersleading to the through holes are arranged to extend toward the inside ofthe package substrate.
 7. A semiconductor device according to claim 6,wherein the memory chip is mounted on the surface of the packagesubstrate, and wherein the semiconductor chip is mounted on a surface ofthe memory chip so as to provide a stacked structure.
 8. A semiconductordevice according to claim 5, wherein with respect to the rows of bondingleads which are formed corresponding to two sides other than the firstside and second side of the memory chip, the pull-out directions of thewiring layers leading to the through holes are distributed to the insideand the outside of the package substrate.
 9. A semiconductor deviceaccording to claim 8, wherein with respect to a length of the bondingleads which are formed corresponding to the first side and the secondside of the memory chip, a length of the bonding leads which are formedcorresponding to two sides other than the first side and the second sideof the memory chip is made short.
 10. A semiconductor device accordingto claim 6, wherein the bonding leads of the package substratecorresponding to the first side and the second side of the memory chipare formed into a rectangular shape such that the longitudinal directionthereof is directed in the extension direction of wires which performthe connection of the bonding leads with the bonding pads of thecorresponding memory chip and the semiconductor chip corresponding tothe bonding leads.
 11. A semiconductor device according to claim 7,wherein the bonding leads which are respectively formed corresponding tothe first side and the second side of the memory chip are bonding leadshaving portions thereof over which wires connected to other bondingleads pass notched.
 12. A semiconductor device according to claim 10,wherein the bonding leads which are respectively formed corresponding tothe first side and the second side of the memory chip are arranged in astaggered manner in two inner and outer rows along the extensiondirection of wires which are connected to the bonding leads, and whereinnotched portions are formed on inner ends of the inside bonding leads.13. A semiconductor device comprising: a semiconductor chip whichincludes bonding pads arranged along at least a first side and a secondside which faces the first side in an opposed manner; and a packagesubstrate which includes bonding leads formed corresponding to the firstside and the second side of the semiconductor chip and externalterminals connected to the bonding leads, wherein the bonding leads haveportions thereof over which wires connected to other bonding leads passnotched.
 14. A semiconductor device comprising: a semiconductor chipincluding bonding pads which are arranged along at least a first sideand a second side which faces the first side in an opposed manner; and apackage substrate including bonding leads which are formed correspondingto the first side and the second side of the semiconductor chip andexternal terminals which are connected to the bonding leads, wherein thebonding leads are arranged in a staggered manner at two inner and outerrows along the extension direction of wires which are connected to thebonding leads, wherein the pull-out direction of wiring layers leadingto respective lead through holes are directed toward the inside of thepackage substrate, and wherein notched portions are formed in inner endsof the inside bonding leads.